In general, semiconductor memory devices for storing data are divided into volatile memory devices, which are likely to lose their data when the power supply is interrupted, and nonvolatile memory devices, which can retain their data even when the power supply is interrupted. Compared to other nonvolatile memory technologies, e.g., disk drives, nonvolatile semiconductor memories are relatively small. Accordingly, nonvolatile memory devices have been widely employed in mobile telecommunications systems, memory cards, etc.
Recently, nonvolatile memory devices having silicon-oxide-nitride-oxide-silicon (SONOS) structures, e.g., SONOS-type nonvolatile memory devices, have been proposed. The SONOS-type nonvolatile memory devices have thin cells which are simple to manufacture and can be easily incorporated, e.g., into a peripheral region and/or a logic region of an integrated circuit.
A SONOS-type nonvolatile semiconductor memory device according to the Background Art will be described with reference to FIG. 1. The SONOS-type nonvolatile semiconductor memory device 10 includes: a silicon substrate 6 having doped source and drain regions 5; a tunnel oxide layer 1; a nitride layer 2 on the tunnel oxide layer 1; a top oxide layer 3 on the nitride layer 2; and a polycrystalline silicon (polysilicon) gate layer 4 on the oxide layer 3. Together the layers 1, 2 and 3 define an oxide-nitride-oxide (ONO) structure 1/2/3.
In operation, electrons or holes are injected into the tunnel oxide layer 1 from the inversion region induced between the source 5 and drain 5. The nitride layer 2 is a charge trapping layer that traps electrons or holes that penetrate through the tunnel oxide layer 1. The top oxide layer 3 is provided to prevent any electrons or holes that escape the trapping layer 2 from reaching the polycrystalline silicon layer 4 during write or erase operations. The structure 10 can be described as a stacked SONOS-type cell.
When the gate electrode 4 is positively charged, electrons from the semiconductor substrate 6 become trapped in a region 7 of the nitride layer 2. Conversely, when the gate electrode 4 is negatively charged, holes from the semiconductor substrate 6 become trapped in the region 7. The depiction of the region 7 in FIG. 1 is asymmetric with respect to a vertical center line (not depicted) of the SONOS-type semiconductor memory device 10. FIG. 1 assumes a situation in which the drain corresponds to the region 5 at the right side of FIG. 1 while the source corresponds to the region 5 at the left side of FIG. 1, with the drain also assumed to be biased at a higher voltage than the source. Accordingly, electrons/holes accumulate near the higher-biased drain.
The electrons or the holes trapped in the region 7 can change the threshold voltage of the entire nonvolatile semiconductor memory device. When the gate threshold voltage reaches a predetermined level, i.e., when the current of a channel is reduced to a sufficiently low level, the programming process stops. The threshold voltage Vth is set to a value at which a bit ‘0’ can be distinguished consistently from a bit ‘1’ for data that has been retained a predetermined amount of time (rephrasing, Vth is set to a value at which a predetermined amount of data retention time can be achieved consistently).
Since an ONO structure (1/2/3) exists above the entire channel region, the stacked SONOS-type cell 10 has a high initial threshold voltage Vth (and corresponding high power consumption) and a high program current. Because of the high threshold voltage Vth and the high program current, it is difficult to embed the stack SONOS in system-on-a-chip (SoC) products which demand low power consumption.
In addition, in the stacked SONOS-type cell 10, electrons trapped in the nitride layer 10 can move laterally along the nitride layer, and thus an erase operation may not be completely performed. If programming operations and erase operations are repetitively performed, the threshold voltage Vth of on-cell (erased cell) can increase, which can reduce the on-cell current and read speed.
To address such problems, SONOS-type devices having various structures have been developed in the Background Art, e.g., the local SONOS-type cell 20 shown in FIG. 2. The SONOS-type cell 20 includes: a silicon substrate 26 having doped source and drain regions 25; a tunnel oxide layer 21 on the substrate 26; nitride layer segments 28 and 29 on the tunnel oxide layer 21; a dielectric layer 27 on the tunnel oxide layer 21; a top oxide layer 23 on the nitride layer segment 28, the dielectric layer 27 and the nitride layer segment 29; and a polycrystalline silicon gate layer 4 on the top oxide layer 23.
In contrast to FIG. 1, where the tunnel oxide layer 1 entirely covers the channel region between the source and drain regions 5, the nitride layer (not depicted, but from which the nitride layer segments 8 and 9 were formed) has had a center section removed, resulting in the nitride layer segments 8 and 9. By separating the nitride layer segments 8 and 9 (and filling the resulting gap with the dielectric layer 27), trapped electrons that would otherwise be able to migrate laterally along the nitride layer 2 of FIG. 1 are prevented from moving from the nitride layer segment 8 to the nitride layer segment 9 and vice versa. This improves the on-cell current and read speed. The separated ONO structures 21/(28 or 29)/23 are the reason for describing the SONOS-type cell 20 as a local SONOS-type cell. However, because a thick dielectric structure (layers 21, 27 and 23) exists above the entire channel region, the local SONOS-type cell 20 still has a high initial threshold voltage Vth.
FIG. 3 is a diagram showing another local SONOS-type cell 30 according to Background Art. The local SONOS-type cell 30 includes: a silicon substrate 26 having doped source and drain regions 25; an oxide layer 32 on the substrate 26, the oxide layer 32 having branches 34 and 38; nitride layer segments 36 formed between pairs of oxide layer branches 34 and 38, respectively; and a polycrystalline silicon gate layer 40. Each nitride layer segment 36 sandwiched between oxide branches 34 and 38 defines an ONO structure 34/36/38. The portion of the oxide layer 32 between the ONO structures is significantly thinner than the corresponding dielectric structure 21/27/23 in the local SONOS-type cell 20 of FIG. 2, which can improve (namely, lower) the threshold voltage Vth.
The operating characteristics of the local SONOS-type cell 30 can vary considerably depending on the length (L) of the overlap between the ONO structure 34/36/38 and the gate layer 40, where L is substantially the same as the length of the nitride layer segment 36. Accordingly, it is important to minimize variation in the length of the overlap between the ONO structures 34/36/38 and the gate 40.
Photolithography is used to define the length of the ONO structures 34/36/38 in FIG. 3. During the photography portion of the photolithography process, misalignment can occur, resulting in significant overlap variation.
To help depict the misalignment problem, FIGS. 4A and 4B are provided. FIG. 4A is a cross-section (of an intermediate structure produced at one stage in the manufacture of the SONOS-type cell 30 in FIG. 3) showing substantial alignment. FIG. 4B is a similar cross-section showing significant misalignment. To help convey the relationship between FIG. 3 and FIGS. 4A and 4B, regarding the arrangement of layers in FIG. 3 underneath the bracket 42, a corresponding arrangement of layers in FIG. 4 is located underneath bracket 442.
The intermediate structure 400 in FIG. 4A includes: a silicon semiconductor substrate 402; an ONO structure 404 on the substrate 402; a polycrystalline silicon layer 406 on the ONO structure 404 and on the substrate 402; and a photo resist (PR) 407 on the polycrystalline silicon gate layer 406. A gap 408 is depicted in the photo resist layer 407. The gap 408 is aligned so that when the underlying cross-hatched 410 is removed, the resulting overlap between the remaining ONO structures 404 and the gate layer 406 is substantially equal, as indicated by each overlap having the length L1.
FIG. 4B, in contrast, is a cross-section of an intermediate structure 420 according to the Background Art that corresponds to the intermediate structure 400, albeit suffering significant misalignment. The intermediate structure 420 includes: a silicon substrate 422; an ONO structure 424 on the substrate 422; a polycrystalline layer 426 on the ONO structure 424 and the substrate 422; and a photo resist layer 427 having in it gaps 428. When the cross-hatched areas 430 underneath the gaps 428 are removed via etching, the resulting ONO structures 424 will not be of the same width, as indicated by the lengths L2 and L3, where L2<L1<L3. As an example, where L1=150 nm, significant misalignment can produce lengths of about L2=100 nm and L3=200 nm. Such variation in the overlap lengths causes variation in the threshold voltages to be exhibited by the local SONOS-type cells, e.g., depending upon whether the cell has overlap L2 or L3.
A type of overlapped, but electrically separate, gate electrode architecture is known, e.g., U.S. Pat. No. 6,388,293 to Ogura et al. (the “Ogura patent”). Background Art FIG. 5 of the present application corresponds to FIG. 11 of the Ogura patent except for using 500-series numbering rather than 100-series numbering. The overlapped but electrically separate structure 500 of Background Art FIG. 5 includes: a semiconductor substrate 510 having doped source/drain regions 521 and 522; a three-strata gate insulator 532 formed on the substrate 510; a lower gate electrode 542 formed on the gate insulator 532; another gate insulator 531 formed on the substrate 510, the side edge of the other gate insulator 532, and the side edge and a portion of the top of the lower gate electrode 542; and an upper gate electrode 541 formed on the gate insulator 531. The three-strata gate insulator 532 can be an ONO structure, namely layer 532A being an oxide, layer 532B being a nitride and layer 532C being an oxide; other combinations of materials for the three strata are disclosed as well the Ogura patent. The three-strata gate insulator 532 is self aligned with the lower gate electrode 542. The lower gate electrode 542 and the upper gate electrode 541 are electrically separated, i.e., they are not electrically connected together. Moreover, the Ogura patent teaches that the electrical potential supplied to the lower gate electrode 542 should be large while the electrical potential supplied to the upper gate electrode 541 should be as small as the gate threshold voltage.